This invention relates to an integrated circuit and more particularly to a protection circuit using shallow trench isolation technology.
Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A typical circuit used to determine sensitivity of the semiconductor circuit to human handling includes a capacitor and resistor that emulate a human body resistor-capacitor (RC) time constant. The capacitor is preferably 100 pF, and the resistor is preferably 1500 xcexa9, thereby providing a 150-nanosecond time constant. A semiconductor device is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, the capacitor is initially charged to a predetermined stress voltage and discharged through the resistor and the semiconductor device. A post stress current-voltage measurement determines whether the semiconductor device is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge.
A charged-device ESD test is another common test method for testing semiconductor device sensitivity. This method is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The semiconductor device forms a capacitor above a ground plane that is typically 1-2 pF. A low impedance conductor forms a discharge path having an RC time constant typically two orders of magnitude less than a human body model ESD tester. In operation, the semiconductor device is initially charged with respect to the ground plane to a predetermined stress voltage. The semiconductor device is then discharged at a selected terminal through the low impedance conductor. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the semiconductor device approaches that of the initial stress voltage.
A particular problem of design of silicon-controlled rectifier (SCR) input protection circuits arises with advanced shallow trench isolation (STI) processes. The problem will be explained in detail with reference to the section view (FIG. 1A) and the schematic diagram (FIG. 1B) of an SCR protection circuit of the prior art. The SCR includes a PNP bipolar transistor having an emitter 108 connected to an external terminal 100 via lead 118. The base region 114 of the PNP transistor is electrically connected to a heavily doped N+ region 106 by the parasitic resistance 115 of N-well region 114. The collector 130 of the PNP transistor is formed in the P-substrate 116. An NPN bipolar transistor has a collector 114 in common with the PNP base and a base 130 in common with the PNP collector. The NPN bipolar transistor has an emitter 124 connected to a Vss reference supply terminal 120. The protection circuit further includes a metal-oxide semiconductor (MOS) transistor having a drain 112, gate 122 and source 124. The drain 112 of the metal-oxide semiconductor (MOS) transistor 122 is connected to N+ region 106 through parasitic N-well resistors 115 and 111.
In operation, the SCR is activated by application of a positive electrostatic discharge pulse at the bond pad or external terminal 100 with respect to the Vss reference supply terminal 120. This positive pulse initially induces avalanche conduction of the MOS transistor due to a high electric field between the drain region 112 and the gate region 122. This avalanche conduction injects positive current directly into the base region 130 of the NPN transistor. This NPN transistor base current subsequently induces NPN transistor collector current through N-well resistor 114. This NPN transistor collector current forward biases the PNP transistor base and produces base current. The PNP transistor base current, therefore, initiates PNP transistor conduction and consequent regenerative SCR conduction as is well known in the art. A particular problem arises when highly doped regions such as N+ region 112 are physically surrounded by shallow trench isolation (STI) regions such as regions 102 and 104. These STI regions are typically greater than 1.0 micrometer deep and, therefore, serve to electrically decouple the transistors of the SCR having junction depths less than 0.3 micrometers. This decoupling increases the PNP transistor base resistance as well as the resistance between the MOS transistor and the SCR, thereby increasing the trigger or activation threshold of the SCR. The circuit of the prior art (FIG. 1A) attempted to resolve this problem by adding gate region 110. This gate region 110 provided a continuous active region of P+ doped region 108, N doped region 128 and N+ doped region 112 without an intervening STI region. Although this technique improved the decoupling problem, it introduced a thin oxide region between gate region 110 and N+ region 112 that was particularly susceptible to damage under high voltage ESD stress such as charged-device stress.
Referring now to FIG. 2A, there is a section view of another SCR protection circuit of the prior art as disclosed in U.S. Pat. No. 4,939,616, filed Nov. 13, 1989, and a corresponding schematic diagram (FIG. 2B). The SCR includes a PNP bipolar transistor having an emitter 208 connected to an external terminal 200. The base region 214 of the PNP transistor is electrically connected to a heavily doped N+ region 206 by the parasitic resistance 215 of N-well region 214.
The collector 230 of the PNP transistor is formed in the P-substrate 216. An NPN bipolar transistor has a collector 214 in common with the PNP base and a base 231 in common with the PNP collector. The NPN bipolar transistor has an emitter 224 connected to a Vss reference supply terminal 220. The protection circuit further includes a lateral parasitic NPN bipolar transistor having a collector 212, thick-oxide isolation region 230 and emitter 224. Other thick-oxide isolation regions are designated 233. A zener diode 209 couples P+ doped region 208 to N+ doped region 212.
In operation, the SCR is activated by application of a positive electrostatic discharge pulse at the bond pad or external terminal 200 with respect to the Vss reference supply terminal 220. This positive pulse initiates avalanche conduction at the reverse biased junction of N+ doped region 212 and P substrate 216. This avalanche conduction develops a voltage drop across N-well region 214 and forward biases zener diode 209. The zener diode conducts the avalanche current into the base 231 of the NPN transistor. The avalanche current in the base region 231 subsequently forward biases the NPN emitter 224, thereby initiating bipolar NPN conduction. This NPN conduction increases PNP transistor base current and, therefore, initiates PNP transistor conduction and consequent regenerative SCR conduction as is well known in the art. A particular problem arises with advanced technologies. The trigger or activation threshold of the SCR is primarily determined by the avalanche threshold of a junction formed by N+ region 212 and P-substrate 216. This high trigger or activation voltage may be incompatible with thin gate oxides and STI of advanced technologies. This increased trigger or activation threshold produces high voltage transients at the bond pad 200 and may cause premature failure of the internal circuit.
These problems are resolved by a structure with a lightly doped substrate having a first conductivity type and a face. A first lightly doped region has a second conductivity type and is formed within the lightly doped substrate. A first heavily doped region has the first conductivity type and is formed at the face and extends to a first depth within the first lightly doped region. A second heavily doped region has the second conductivity type and is formed at the face abutting the first heavily doped region. The second heavily doped region extends to a second depth and is at least partly within the first lightly doped region. A first isolation region is formed at the face, abutting at least one of the first and second heavily doped regions. The first isolation region extends to a third depth that is greater than either of the first and the second depths.
The present invention eliminates premature gate oxide degradation in a protection circuit due to high voltage ESD stress. Effective coupling of transistors is maintained for advanced processes such as STI.